Wideband digital downconversion (DDC) is often required as the first stage in any digital signal processing system prior to selective filtering or channelisation stages, the implementation of which would otherwise be compromised by the high input sample rate, typically GSPS (Giga samples per second).
Basic WB DDC operation
The very high GSPS ADC sample rates require a parallel, de-multiplexed data architecture within the FPGA and this wide parallelisation makes an efficient implementation extremely challenging. RF Engines have developed novel techniques to implement this real-time function on tightly constrained FPGA resources, whilst still providing flexibility in the form of customised and parameterised soft-controlled core functions. In particular, the problems of parallelism have been solved in various custom implementations of our standard IP blocks.
The general form of a DDC in a typical application is shown below:
Case Study 1 : Wideband Receiver in Small Footprint
A 1.3Ghz bandwidth signal was sampled at 2.66GSPS with an ENOB of less than 7 bits and SFDR of 52dBc. Operating on this input, The RF Engines DDC core output an effective complex signal pass-band of 500MHz with an SFDR of 60dBc. Passband ripple of < ±0.1dB was achieved at the output, at a data rate of 666MSPS. Parallelism of 16 was reduced to 3, whilst filter output resolution was increased to 8 bits at the output. Resource usage was approximately 50%[w1]of a Xilinx Virtex SX95T and the core power consumption was estimated to be an extremely low at 500mW[w2].
Case Study 2 : Programmable Wideband Re-sampler
A GHz region IF signal was sampled at a programmable 2.2, 2.1, 1.875 and 1.333 GSPS,with up to 26 selectable re-sampled filtered outputs, ranging from re-sampling factors of 2 to1280. Output passband (with >60dB stop band rejection) varied from 1.2MHz to 880MHz according to configuration. Input Parallelisms of 16 were reduced to output parallelisms of 4 or 2[w3] with output sample resolutions of 9 to 13 bits depending on factor selected. Filter pass band ripple was less than ±0.1dB. The core used approximately 60% of an Altera Stratix
III EP3SL150, and the architecture was optimised to make best use of the vendor specific DSP resources. Customised Models were delivered in 4 weeks and a verified Core implementation was delivered in 13 weeks.
Features
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Input sample rates in excess of 3GSPS
- Output bandwidths from Hz to 100’s of MHz
- Input Parallelism of 1-16, with any output parallelism appropriate
- Run-time programmable fractional re-sampling
- Multiple selectable filter shapes may be provided
- Experienced consultative services offers optimisation to minimise resource usage without compromising performance
Applications
- Telecommunications basestations
- Satellite ground stations
- Software defined radio
- Military communications systems
- Radio monitoring systems
Models
The Wideband DDC is available as Modelsim compiled VHDL and more details can be obtained from our sales team who will be happy to process your enquiry.
Contact details can be found on the Contacts page.