RF Engines Ltd (RFEL) provide a range of high specification FPGA-based Pipelined Fast Fourier Transform (FFT) cores. The pipelined or "streaming" architecture ensures that all cores can process back-to-back blocks of time-domain input data in real-time. FFT parameters such as radix, processing parallelism and bit growth can be tailored by RFEL to suit each application resulting in the most optimal design in terms of silicon, power and performance.

Complementary core options include polyphase and standard windowing, input buffering for single or multiple channel processing, input buffering for overlapped FFT processing, bit-reversal and 100% efficient real input FFT processing.

The designs are sold as Intellectual Property (IP) cores to equipment manufacturers and allow a low cost and reduced risk route to a faster design cycle.




Overview of the Range
The range includes the following types of FFT core:

1) HiSpeed FFT cores implement a Pipelined radix-2 Decimate In Frequency (DIF) algorithm using a single data path pipeline. This 'parallelism of 1' can typically accept complex time-domain data at a maximum continuous rate (and hence signal bandwidth) of 100MHz, depending on the FPGA target. The HiSpeed architecture is designed to be the smallest of the Vectis range in terms of logic and multiplier resource, and is matched in terms of real-time bandwidth to currently available 12-bit and 14-bit Analogue to Digital Converter (ADC) devices. Product Page

2) QuadSpeed FFT cores implement a Pipelined radix-2 DIF algorithm with a parallelism of 4. These cores can typically accept complex time-domain data at a maximum continuous rate of 400MHz. A QuadSpeed FFT core will consume roughly the same memory resource, two to three times the logic and three to four times the multiplier resource required by a HiSpeed core of the same transform length and arithmetic precision. Product Page

3) Matrix FFT cores implement a mixed-radix algorithm with a parallelism of 2. These cores can typically accept complex time-domain data at a maximum continuous rate of 200MHz. Transforms of any length can be implemented, providing sufficient FPGA resource is available. Product Page

4) HyperSpeed FFT cores implement a mixed-radix algorithm with a parallelism of '2M' and a transform length of 'M x N'. 'M' and 'N' can be any integer, though integer powers of two provide the most silicon-efficient implementations. A HyperSpeed core with a parallelism of 8 can typically accept complex time-domain data at a maximum continuous rate of 800MHz. Product Page

5) HyperLength FFT cores implement a mixed-radix algorithm that requires RAM external to the FPGA to achieve large transform lengths. Both transform length and maximum sustained processing bandwidth are dependent on the type and configuration of external RAM. Product Page

The Xilinx FFT Library includes a selection of more than sixty HiSpeed and QuadSpeed FFT cores targetted at Xilinx Spartan III, Virtex II, Virtex II Pro, and Virtex IV devices. The cores are supplied on a single CD, and include a site licence for R&D development purposes, and a licence for use of the cores in manufactured product. Product Page

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