RFEL signal processing iq : fpga expertise

RFEL

Video Processing

IP Cores

Distortion Correction

The optimised Distortion Correction IP core is a real-time, ultra low-latency, best-in-class solution for the in-line correction of either barrel or pin-cushion radial lens distortion. Use the enhanced core to quickly add competitive advantage to your FPGA based vision systems, producing undistorted wide angle scenery or pre-distorted imagery for display on curved surfaces. Accelerate development, enhance results and boost product capability with no compromise.

Lens Distortion Correction Photograph examples

Features

  • Ultra low latency at less than 6ms
  • OpenCV 2.4 radial & tangential distortion correction
  • Correct radial distortions up to 25%
  • Pre-distorts for 'flat' appearance on curved displays
  • Digital zoom, for regions of interest
  • Supports full colour at HD and high frame-rate
  • Optimised for size, weight and power (SWaP) and cost sensitive applications

Applications
The Distortion Correction core is a cost-effective solution which provides an undistorted and extremely wide angle of view from standard lenses. It is an in-line, ultra low-latency solution, well suited to new builds and system upgrades. It has applications in surveillance, reconnaissance, unmanned and piloted air systems, driver and pilot aids and underwater systems. Simulation, virtualisation and user-interface designs will also benefit from the core's ultra low-latency, to project pre-distorted imagery so that it appears undistorted when viewed on curved and cylindrical surfaces; and to act as an essential pre-conditioner for image stitching applications.

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Lens Distortion Correction Block Diagram

RFEL's DC FPGA IP core is a real-time radial and tangential distortion correction processing module, which is also capable of pre-distorting image frames for projection and natural viewing on curved screens. With its processing chain implemented entirely in FPGA resources, the DC IP core is ideal for diverse FPGA or SoC based vision processing applications. The IP core presents a combination of two winning elements: easy access for modelling and simulation, by virtue of its compliance with OpenCV, and adoption of a world-class FPGA architecture, implemented by RFEL's highly experienced design team.

Sub-item

Description

Performance Corrects radial distortions of up to 25%
Algorithm Supports all 12 parameters specified by OpenCV 2.4 'undistort' function
Interpolation Bi-linear
Interfaces AX14 Stream and Memory interfaces
Input Format (1) Up to 16 bit mono, 16 bit YCbCr 422, 24 bit YCbCr 444 and 24 bit RGB
Output Image Format Identical to input
Resolutions 16 x 16, to 1280 x 720
Frame Rates Up to 60 fps, progressive
Latency Typically < 6ms
Clock Frequency (2)/td> 200MHz
Maximum Req. Memory B/W Application dependent, however DDR2 and DDR3 devices are typically supported
Supported Devices

Xilinx Zynq TM -7000 / ArtixTM -7 / Kintex TM -7

Altera Arria ® SoC to be certified soon

Reference Design RFEL HALO TM RPDS based pre-integrated Quick Start hardware dev. kit
Delivery Xilinx ISE net-list or Vivado IP builder

(1) Delivered formats factory configured
(2) Xilinx Kintex targets

Platform Support

  • Altera
  • Xilinx

Customisation
RFEL offers a range of options and additional IP blocks which allow this product to be delivered in the configuration best suited to the precise needs of a particular application.
For more demanding requirements, deeper systems integration, or in cases where further customisation is required, RFEL also provides design services to help with the process of integration.

Along with the netlist for each IP core, RFEL supplies a comprehensive set of models, scripts and test benches for simulation and synthesis.

Supplied Item

Description

Design

Netlist

Constraints File

Vendor Specific

Instantiation Template

VHDL

Verification

VHDL test bench including Modelsim script and test data files.

Compiled RTL VHDL model.

Bit-true MATLAB model and scripts.

Implementation reports.

Implementation
Depending on configuration, the DC IP core requires a frame buffer memory. All interfaces (video, memory and control) are implemented as flexible AX14 compliant interfaces or similar. As with all RFEL IP cores, the DC IP core is supported by a 'bit-true' MatlabTM model, which behaves identically to the core and can be used to verify anticipated performance. Contact RFEL for options on evaluating performance with sample video sequences, or to ask about out HALOTM RPDS development platform, pre-integrated with DC for out-of-the-box demonstration and accelerated product development.

Ordering Information

Item

Part Number

DC Xilinx Zynq ® -7020 IP10-01-ZA
DC Xilinx Zynq ® -7030/45 IP10-01-ZK
DC Xilinx Artix ® -7 IP10-01-A7
DC Xilinx Kintex ® -7 IP10-01-K7
Altera ArriaV SoC 5ASXB3 Contact RFEL sales

The configuration used to produce the FPGA Resource Estimate (below) was:
Number of distortion parameter: 8
Cylindrical projection: ON

FPGA Family Xilinx Spartan 6 Altera Cyclone IV Xilinx Zynq 7045
FPGA Part No SLX75-2FGG676 EP4CGX110DF31C7 -
Registers 11255 6942 18504
LUTs 6164 7153 9697
Block RAMs 21 - 109
M20K RAMs - 23 -
DSP48Es 40 - 47
DSP Blocks - 42 -

 

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