RFEL signal processing iq : fpga expertise

Signal Processing

IP Cores

Fractional Rate Resampler - RFEL

Fractional Rate Resampler

RFEL’s flexible rate resampler architecture supports up-sampling or down-sampling of many channels simultaneously and allows the rate change to be selected with a resolution of less than one Hertz. When operating on multiple input channels, the architecture treats each channel independently allowing different input/output sampling rates and rate changes. Furthermore, the rate change required for each channel can be updated at run-time, without affecting the operation of other channels.

Fractional Rate Resampler Image

Features

  • Silicon usage minimised for each application
  • Supported by bit-true MATLAB models
  • Xilinx and Altera FPGA devices supported
  • Adjustable bit widths and bit growths
  • Fractional architecture allows precise sample rate changes to sub-Hertz resolution
  • Architectures available for up and down conversion
  • Simultaneous resampling of multiple channels (potentially thousands)
  • Resampling rates reconfigurable at run-time
  • Multi-channel aggregate sample rates up to 200 MHz
  • High performance filtering reduces aliasing effects
  • Fully pipelined design

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Resampler Block Diagram

Parameter

Specification

Factors Large values of L and M are possible up to a modulus of 232
Resolution Based on a 32-bit modulus and a 200 MHz input sample rate, sub-Hz rate resolutions are acheivable
Number of Channels The resampler can be implemented using resource sharing techniques that allow serveral independent input channels to be interleaved and processed by a single resampler. Each channel can have its own independent fixed or programmable rate change
Resource Sharing For an overall reduction in sample rate, if the input sample rate is lower than the FPGA clock rate, filter arithmetic can be shared reducing FPGA resources even further
Multiple Channels For multiple parallel channels requiring the same resampling factor, resource sharing can be used resulting in architecture that consumes less resources than using multiple parallel cores
Sub-Sample Delay If L and M set to be the same value, then start phase (a third runtime programmable parameter in the range 0 to M-1) can be programmed to enable sub-sample delays to be implemented
Run-time Parameters L, M and the start phase can all be made runtime programmable

Platform Support

  • Altera
  • Xilinx

Customisation
For more demanding requirements, deeper systems integration, or in cases where further customisations are required, RFEL also provides design services to help with the integration task.

Along with the netlist for each IP core, RFEL supplies a comprehensive set of models, scripts and test benches for synthesis and simulation.

Supplied Item

Description

Design

Netlist

Constraints File

Vendor specific

Instantiation Template

VHDL

Verification

VHDL test bench including Modelsim script and test data files.

Compiled RTL VHDL model.

Bit-true Matlab model and scripts.

Implementation reports.

Warranty
For peace of mind, RFEL provides a twelve month warranty as standard. If required, this can be extended as part of a contract at a reasonable extra cost.

Support
RFEL understands that customers might need some support in integrating the IP cores into their systems, and so offers support packages that can be separately booked.

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