RFEL signal processing iq : fpga expertise

Signal Processing

IP Cores

Filters

Distributed Half Band Filter (DHBF)

The Distributed Half Band Filter is a down-convert and decimate filter, primarily intended for use as the first stage in very high sample rate DSP systems. Data is presented at the DHBF input from a high speed sampling system (typically an ADC and anti-aliasing filter) and the input signal is down-converted to base-band with the frequency range +/- fs/4 (where fs is the input sample rate).

DHBF Wavelength Image

- Proprietary techniques implement the DHBF architecture onto an FPGA device to optimise speed and silicon usage.

- Half Band Filter characteristics can be specified over a wide range with regard to side-lobe (stop-band) level and filter order.

- Higher order (sharper) filters will typically increase silicon usage, but the flexible architecture of the DHBF will minimise silicon usage for implementation.

- With a complex output as standard, the core can be used to convert from real data to complex, or with an inverse implementation for complex to real conversion.

Features

  • Complex fs/4 down-conversion from IF to baseband for odd and even Nyquist regions
  • Half band filtering to remove aliases
  • Decimation by two
  • Half band filter can be specified for stop-band attenuation and filter order
  • Can be used in critically-sampled or over-sampled systems
  • Provides a high performance front-end for the RFEL PFT or FFT architectures
  • Various data input bit widths can be implemented
  • Fully synchronous design
  • Easy migration to most FPGA vendors’ devices and architectures

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DHBF Block Diagram

DHBF Specification

Parameter

Specification

Alias Free RF Input 0.1 to 1.1 GHz
Alias Free Bandwidth 1.0 GHz (83.33% Nyquist)
Alias Free Frequency Range 0.1 to 1.1GHz (1st Nyquist)
Input Sample Rate 2.4 Gsps
Output Sample Rate 1.2 Gsps
Input Bit Width 10 bits
Output Bit Width 16 bits (I) + 16 bits (Q)
Stop Band Rejection >=65 dB
SFDR >= 65 dB
Pass Band Ripple <+/- 0.01 dB

iDHBF Specification

Parameter

Specification

Input Data 1.2 Gbps complex
Input Alias Free Bandwidth 1.0 GHz (-0.5 to +0.5 GHz)
Output Data 2.4 Gbps real
Input Width 16 bits (I) + 16 bits (Q)
Output Width 14 bits
Output Bandwidth 0.1 to 1.1 GHz
Stop Band Rejection >= 65 dB
SFDR >= 65 dB
Pass Band Ripple <+/- 0.01 dB

Platform Support

  • Altera
  • Xilinx

Customisation
RFEL offers a range of options and additional IP blocks which allow this product to be delivered in the configuration best suited to the precise needs of a particular application. For more demanding requirements, deeper systems integration, or in cases where further customisation is required, RFEL also provides to help with the process of integration.

In addition to the netlist for each IP core, RFEL supplies a comprehensive set of models, scripts and test benches for simulation and synthesis.

Supplied Item

Description

Design

Netlist

Constraints File

Vendor-Specific

Instantiation Template

VHDL

Verification

VHDL test bench including Modelsim script and test data files

Compiled RTL VHDL model

Bit-true MATLAB model and scripts

Implementation reports

Warranty
For peace of mind RFEL provides a twelve month warranty as standard. If required, this can be extended as part of a contract at a reasonable extra cost.

Support
RFEL understands that customers might need some support in integrating the IP cores into their systems, and so offers support packages that can be booked separately.

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