RFEL signal processing iq : fpga expertise

Signal Processing

IP Cores

Fourier Analysis

QuadSpeed

RFEL’s QuadSpeed FFT cores process complex input data in continuous real time, with no gaps in the data and at complex data rates in excess of 500 Msps. They are highly optimised in terms of their memory, multiplier and logic use. Integral interleaving enables several channels to be multiplexed through the same core. Real-time FFT length switching is also a valuable feature, supporting back-to-back variable FFT frame length inputs.

Features

  • Continuous real-time processing of complex data in excess of 600 Msps
  • Save resources with multiple input interleaving and back-to-back frame FFT length switching
  • Optimised for the speed silicon trade-off
  • Optional Input Buffer and Bit Reverser
  • Programmable length
  • Continuous real-time processing, compatible with 1 Gsps ADC using RFEL’s optional DHBF
  • Interleave multiple inputs, through one FFT
  • 8 to 128K-point versions available (longer lengths by request)
  • Bit-width and bit-growth adjustable (factory setting)
  • Twiddle-width adjustable (factory setting)
  • Targeted at Xilinx and Altera FPGA families

Please enter the word you see in the image below:


QuadSpeed FFT Block Diagram

Parameter

Specification

Input Data Rate To ~600 Msps
Input Type

1x Complex

Input Interleaving 4 interleaved inputs (more available on request)
Input Buffer Optional, including optional reorder
Input Window Optional
Internal Parallelism 2 x complex
FFT Length 8 to 128k-pt
FFT Mode FFT or Inverse FFT (build or run-time configurations
Length Adaptation Switchable (option back to back switching at run-time)
Output Order Scrambled or reordered to natural

Platform Support

  • Altera
  • Xilinx

Customisation
RFEL offers a range of options and additional IP blocks which allow this product to be delivered in the configuration best suited to the precise needs of a particular application. For more demanding requirements, deeper systems integration, or in cases where further customisation is required, RFEL also provides Design-IQTM design services to help with the process of integration.

Deliverables
In addition to the netlist for each IP core, RFEL supplies a comprehensive set of models, scripts and test benches for simulation and synthesis.

Supplied Item

Description

Design

Netlist

Constraints File

Vendor Specific

Instantiation Template

VHDL

Verification

VHDL test bench including Modelsim script and test data files.

Compiled RTL VHDL model.

Bit-true Matlab model and scripts.

Implementation reports.

Warranty
For peace of mind RFEL provides a twelve month warranty as standard. If required, this can be extended as part of a contract at a reasonable extra cost.

Support
RFEL understands that customers might need some support in integrating the IP cores into their systems, and so offers packages that can be booked separately.

The following implementation figures are for the following QuadSpeed FFT configuration:

  • 8 to 1k-point variable transform
  • 2 interleaved complex inputs
  • 12-bit in
  • 16-bit out
  • 18-bit twiddles
  • 250MHz complex data rate

FPGA Family

Xilinx Virtex 7

Altera Stratix 5

FPGA Part No

XC7V585t-1FFG1157

5SGSMD4E1H29C1

Registers

3251

11960

LUTs

2478

2691

18Kb Block RAMs

10

-

36Kb Block RAMs

19

-

M20K RAMs

-

38

DSP48Es

32

-

DSP Blocks

-

16

FMax

>250MHz

>250MH

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