RFEL signal processing iq : fpga expertise

Signal Processing

IP Cores

Fourier Analysis

HyperLength

RFEL’s HyperLength FFT design allows the implementation of very long transforms in FPGA by utilising external RAM. The architecture uses a pair of pipeline FFTs to implement an N point and an M point DFT, which, together with data re-ordering and twiddle factor application, form an (N x M)-point FFT. External RAM is used to perform the required data re-ordering stages. Twiddle factors are generated arithmetically using logic within the FPGA rather than being stored in external memory.

The driving factor behind the FPGA choice for the HyperLength FFT is often not the resource required to implement the processing, but the bandwidth limits of the available external RAM devices and the I/O required connecting them.

Features

  • Very long FFT lengths, not normally possible in FPGA using internal memory
  • Maximises silicon efficiency and performance for each application
  • Continuous real-time processing up to 600 Msps complex
  • 128K to 256 Million points with external memory
  • Twiddle bit and bit growth adjustable (factory setting)
  • Fully pipelined
  • Integer powers of two or prime length FFTs

Please enter the word you see in the image below:


HyperLength FFT block diagram

Parameter

Specification

Input Data Rate To ~600 Msps
Input Type 1x Complex
Input Interleaving

Optional

Input Buffer Optional, including optional reorder (build time)

Internal Window

Optional, user defined type
Internal Parallelism Flexible, defined at build time, sample rate dependent
FFT Length Notionally to 1G-point (platform memory dependent)
FFT Mode FFT or Inverse FFT (build or run-time configurations)
Length Adaptation Switchable (optional run-time back-to-back switching)
Output Order Scrambled) or reordered to natural
External Memory Support Yes

Platform Support

  • Altera
  • Xilinx

Customisation
RFEL offers a range of options and additional IP blocks which allow this product to be delivered in the configuration best suited to the precise needs of a particular application. For more demanding requirements, deeper systems integration, or in cases where further customisation is required, RFEL also provides Design-IQTM design services to help with the process of integration.

Supplied Item

Description

Design

Netlist

Constraints File

Vendor Specific

Instantiation Template

VHDL

Verification

VHDL test bench including Modelsim script and test data files.

Compiled RTL VHDL model.

Bit-true Matlab model and scripts.

Implementation reports.

Warranty
For peace of mind RFEL provides a twelve month warranty as standard. If required, this can be extended as part of a contract at a reasonable extra cost.

Support
RFEL understands that customers might need some support in integrating the IP cores into their systems, and so offers support packages that can be booked separately.

The following implementation figures are for the following HyperLength FFT configuration:

  • 1M point transform
  • 16-bit in
  • 24-bit out
  • 18-bit twiddles.
  • 200MHz data rate

FPGA Family

Xilinx Virtex-6

FPGA Part No

XC6VSX315T-1

Registers

9615

LUTs

6798

18Kb Block RAMs

21

36Kb Block RAMs

33

DSP48Es

76

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