RFEL provides a range of high specification FPGA-based Pipelined Fast Fourier Transform (FFT) cores. The pipeline or streaming architecture ensures that all cores can process back-to-back blocks of time-domain input data in real-time.
FFT parameters such as radix, processing parallelism and bit growth can be tailored by RFEL to suit each application resulting in the most optimal design in terms of silicon, power and performance. Complementary core options include polyphase and standard windowing, input buffering for single or multiple channel processing, input buffering for overlapped FFT processing, bit-reversal and 100% efficient real input FFT processing. The designs provide a low cost and reduced risk route to a faster design cycle.
All of the IP cores come with extensive documentation, bit-true MATLAB models and VHDL testbenches. The IP cores are available for Xilinx and Altera devices. Any other FPGA vendors are subject to adoption.