RFEL signal processing iq : fpga expertise

RFEL

Design Services

FPGA Design

RFEL has a long and successful history in FPGA Firmware development for resource constraint devices. This enables RFEL to implement signal and video processing algorithms into systems and FPGA-devices with even the most demanding of specifications.

In comparison to standard firmware design processes, RFEL's design services help achieve the most optimal algorithm implementation to improve a system’s size, weight and power (SWaP) benchmarks at a competitive price. The implementation of complex signal processing solutions requires a sophisticated design and test methodology to ensure integrated products operate robustly. RFEL has developed and evolved a process through over a decade of hard-won experience, and the high quality of component IP and full systems is a reflection of this invested effort. The process involves significant up-front system modelling of performance to validate the design, fixed-point MATLAB modelling at both the module and system level to facilitate bit-true verification of RTL implementations, gate level testing and final hardware verification. This testing must ensure coverage of all potential input stimuli.

Rigorous testing at the module level ensures that design flaws do not become hidden within the system as this would necessitate lengthy debugging and rework. When a customer approaches RFEL for signal and video processing IP or an implementation, they do this safe in the knowledge that the product has been rigorously tested and validated. This attention to detail de-risks customers’ projects and keeps deliveries to schedule. Furthermore, RFEL can offer fixed price quotations for complex design requests, therefore providing financial control for critical parts of a new product development.

Using RFEL FPGA Firmware Design Services guarantees;

  • Most optimal FPGA implementation regarding performance and resource usage
  • Fixed price
  • Fixed delivery dates
  • Requirements capture and full test coverage
  • Warranty and professional support

FPGA Design Process Flow Chart

RFEL has evolved a high quality, de-risked Firmware development process;

  • Matlab based algorithm development to allow early on performance testing and algorithm optimisation
  • Fixed-point matlab golden reference for early-on customer system development
  • Industry standard PDR, CDR, FAT review stages
  • Large, fully tested and documented internal IP library to enable fast, de-risked developments
  • Multi-stage testing (RTL, gatelevel, hardware) with full coverage and reporting
  • Optional on-site integration support

Please enter the word you see in the image below:


 

 

FPGA Design Block Diagram

The Matlab model is used as a bit-true test reference throughout the design process to ensure full specification compliance.

Platform support

  • Xilinx
  • Altera
  • Lattice
  • Microsemi/Actel

Along with the netlist for each IP core, RFEL supplies a comprehensive set of models, scripts and testbenches for synthesis and simulation.

Supplied Item

Description

Design

Macro netlist.

VHDL source (optional).

Constraints File

Vendor specific.

Instantiation Template

VHDL.

Verification

VHDL test bench including ModelSim script and test data files.

Compiled RTL VHDL Model.

Bit-true Matlab model and scripts.

Implementation reports.

Warranty
For peace of mind, RFEL provide a twelve month warranty as standard.  If required, this can be extended as part of a contract at a reasonable extra cost. 

Support
RFEL understand that customers might need some support in integrating the IP cores into their systems, and so offer support packages of 10 hours each that can be separately booked.

There is currently no data available for this section.

Latest News